1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device that carries out pipe line processing in page mode.
2. Description of the Background Art
FIG. 11 is a block diagram showing a structure of a conventional dynamic type semiconductor memory device.
Referring to FIG. 11, a dynamic type semiconductor memory device comprises a memory cell array 1 having a plurality of memory cells arranged in a matrix of rows and columns, a precharge circuit 2 for holding the potential of the bit line in memory cell array 1 at a predetermined potential at the time of reading, a sense amplifier 3 for amplifying the potential difference appearing on a bit line pair, an I/O control 4 for controlling read/write operation, a column decoder 5 for selecting a desired bit line pair according to column address, a row decoder 6 for selecting a desired word line according to a row address, a preamplifier 7 for amplifying data read out to the bit line pair selected by column decoder 5, a write driver 8 for writing data into a memory cell connected to a desired bit line at the time of writing, an address buffer 9 where address data is entered, an output buffer 10 for providing data read out at the time of reading to an external source, a write buffer 11 for holding data input at the time of writing, a 1/2 Vcc generation circuit 12 for generating a potential that is 1/2 of the power supply potential, a timing signal generation circuit 13 for generating a desired timing signal according to control signals such as RAS and CAS, an address latch 14 for latching the column address applied to address buffer 9, and an output data latch 15 for latching and providing data amplified by preamplifier 7.
FIG. 12 is a diagram showing a portion of memory cell array 1 and the peripheral circuit thereof in FIG. 11.
Referring to FIG. 12, a plurality of bit line pairs BLa and BLb, and word lines X.sub.0 -X.sub.3 crossing the bit line pairs are arranged in memory cell array 1. A memory cell constituted by one set of a memory cell transistor and a capacitor is provided at each crossing of a bit line pair and a word line. Dummy word lines DX.sub.1 and DX.sub.0 are arranged in a direction crossing the bit line pairs, with a dummy cell constituted by one set of a memory transistor and a capacitor formed at each crossing of a dummy word line and a bit line pair. The word line and the dummy word line are connected to row decoder 6. One end of the bit line is connected to precharge circuit 2. Precharge circuit 2 is applied with an equalize signal EQ and a potential V.sub.BL for holding the potential of the bit line pair at a predetermined potential at the time of reading.
The other end of the bit line is connected to sense amplifier 3 and I/O control 4. In I/O control 4, IO buses IOa and IOb for connection to preamplifier 7 and write driver 8 are connected to one of the bit lines of each bit line pair. Transistors Q.sub.5 and Q.sub.6 are provided between the IO bus and the bit line pair. These transistors have the gates connected to column decoder 5.
The read operation of a memory cell will be explained briefly hereinafter with reference to FIG. 12.
According to the input row address, row decoder 6 selects a desired word line so that the corresponding word line attains a predetermined potential. This allows a memory cell to be selected located at the crossing of the selected word line and the bit line pair, whereby information charge held in that memory cell is read to one of the connected bit line pair. This potential is amplified by sense amplifier 3. Then, according to the input column address information, row decoder 5 selects a desired bit line pair. Transistors Q.sub.5 and Q.sub.6 in I/O control 4 of the selected bit line pair are turned on, so that the potentials appearing on the bit line pairs are transferred to data buses IOa and IOb, respectively, to be transferred to preamplifier 7 and read out.
The write operation will be explained hereinafter briefly.
At the time of writing, row recorder 5 selects a desired bit line pair according to row address information. Transistors Q.sub.5 and Q.sub.6 in I/O control 4 connected to the selected bit line pair are turned on so that data buses IOa and IOb are connected to the desired bit line pair. The data applied to write driver 8 is provided as the potential to each bit line of the desired bit line pair via the data bus. Then, row decoder 6 selects a desired word line according to the input row address so that the potential of the selected word line attains a predetermined potential. Thus, the memory transistor in the memory cell located at the crossing of the selected word line and the selected bit line pair is turned on, whereby the potential on the bit line is held in the capacitor of that memory cell to complete the write operation.
FIG. 13 is a diagram for explaining the operation of the relative circuits at a normal read out cycle after the specification of a row address in association with time. The timing chart below the figure shows the transition of each signal corresponding to the above diagram.
The elapse of time of the operation is plotted along the abscissa, and the operation of each component circuit is plotted along the ordinate. A portion of each signal is described in the block diagram of FIG. 11.
Data reading according to a column address is carried out after the data in the plurality of memory cells connected to the word line corresponding to the selected row address are amplified by sense amplifier 3.
In response to the change of signal AL, a column address signal is supplied to and latched in address buffer 9 (0-5 ns). Then, the decoder portion in column decoder 5 corresponding to the column address operates to turn on the transistor in I/O control 4, whereby the potential difference appearing on the bit line pair is transmitted to preamplifier 7. Preamplifier 7 operates simultaneously with the data selection by column decoder 5 to amplify the data of the selected column which is transferred as the potential difference of the bit line. The amplified data is provided to output latch 15 (5-15 ns).
The data provided from preamplifier 7 is latched in output data latch 15. The read out data latched in output data latch 15 is provided to an outer terminal I/O via output buffer 10 (20-35 ns).
Thus, at the time of normal reading operation, reading operation is carried out according to the next new column address data, after the completion of one cycle from the latch of an column address to the output of the read out data.
FIG. 14 is a diagram for explaining the operation of each circuit in a normal writing cycle after the specification of a row address in association with time in a semiconductor memory device of FIG. 11.
Referring to FIG. 14, a column address provided to address buffer 9 is latched by address latch 14 (0-5 ns). Simultaneously, data provided from I/O terminal is supplied to write buffer 11 to be latched in data latch 16 in response to data latch signal DL2 attaining an H level (0-5 ns).
Next, a desired column in the column decoder is selected according to the latched column address to turn on the desired transistor in I/O control 4 (5-15 ns). Simultaneously, the latched write data is transmitted to a data bus by write driver 8, whereby information charge is written into a desired memory cell via the selected bit line (5-15 ns).
In normal writing operation, a subsequent column address data is provided to carry out writing operation after the writing operation according to the input of one column address data is completed.
As described above in association with FIGS. 13 and 14, the reading operation and the writing operation are implemented with 1 cycle of the sequential operations of each component circuits. Therefore, pipe line processing can be carried out by providing a latch circuit for connecting the operations of these component circuits. Pipe line processing in a semiconductor memory device is contemplated to divide the processing steps of the read/write operation request into a plurality of small independent operationable steps for processing a plurality of operation requests subsequently. Corresponding to this definition of pipe line processing, a semiconductor memory device not pipe-lined can be considered a semiconductor memory device that establishes a state capable of receiving a subsequent request every time a reading/writing operation is completed as one step.
Therefore, in a semiconductor memory device that is not pipe-lined, the time period starting from the request of a read/write operation to the semiconductor memory device until the termination of that process (referred to as "memory access time" hereinafter) is substantially equal to a time interval allowing a read/write operation to be requested to a memory (referred to as "memory cycle time" hereinafter). On the other hand, in a semiconductor memory device that is pipe-lined, the memory cycle time is shorter than the memory access time, so that the throughput thereof is greater than that of a semiconductor memory device that is not pipe-lined to result in a reading/writing operation of high speed. This pipe line processing is particularly effective in a dynamic type semiconductor memory device carrying out page mode processing to realize high speed operation.
Page mode of a dynamic type semiconductor memory device will be explained hereinafter with reference to the time chart of FIG. 15.
The fall of external row address strobe signal RAS from the H level to the L level triggers a row address to be supplied. Next, the fall of column address strobe signal CAS from the H level to the L level causes a column address data Col-1 to be supplied. The data of the memory cell specified by the supplied row address and the column address is provided as data Dout-1 via I/O terminal. Signal CAS temporarily returns to the H level and then to the L level again to become active. At this time, address information Col-2 entered as the column address information is supplied to be output as data Dout-2 via I/O terminal. Thus by sequentially changing the level of signal CAS, only the column address can be changed while the row address is held to read out data from a desired memory cell. The page mode processing is an operation that subsequently reads out data in memory cells connected to one word line selected by a row address by sequentially changing the column address, i.e. by switching the gate of an I/O control.
If pipe line processing can be carried out under page mode in a dynamic type semiconductor memory device, high speed operation in reading and the like can be expected.
FIG. 16 is a diagram explaining the operation of each circuit of reading operation carried out by pipe line processing in page mode processing, for example, in association with time in a semiconductor memory device of FIG. 11.
The fall of signal CAS triggers external column address A to be provided to address buffer 9 in response to the change of signal AL, and then to be held in latch 14 (0-5 ns). Read out of columns corresponding to the column address latched in latch 14 is carried out by column decoder 5 (5-15 ns). Simultaneously, preamplifier 7 operates (5-15 ns), so that the read out data is latched in output latch 15 (20-25 ns). In pipe line processing, a new column address is provided to address buffer 9 to be latched in latch 14 in response to the change of signal AL as the subsequent read cycle, simultaneously with the latch of the output latch (20-25 ns). The output data already held in output latch 15 is output via output buffer 10. Simultaneously, the operation of the column decoder and the operation of the preamplifier of the next cycle are carried out in parallel (25-35 ns). Thus, memory cycle time Tc can be reduced with respect to memory access time Ta by providing a partial overlapping operation of a preceding reading cycle and a succeeding reading cycle.
FIG. 17 is a diagram describing the operation in association with time of each circuit when pipe line processing is employed in writing operation in a semiconductor memory device of FIG. 11.
Referring to FIG. 17, when an external column address is provided to address buffer 9 at the first cycle, the column address provided to latch circuit 14 is held therein in response to the change of signal AL2 (10-15 ns). At the next cycle, column decoder 5 selects a desired bit line pair according to the column address latched at the preceding cycle (20-30 ns). The write data held in latch 16 from write buffer 11 is written by write driver 8 to a desired memory cell (20-30 ns). At the same time of these operations, an external column address is provided to address buffer 9 in response to the change of signal AL of the writing operation of the next cycle. Thus, memory cycle time Tc of a writing operation can be reduced by carrying out pipe line processing in writing operation.
FIG. 18 is a diagram for explaining the operation of each circuit in association with time when pipe line processing of another system is carried out at writing operation in the semiconductor memory device of FIG. 11.
This pipe line processing differs from that of FIG. 17 in that the column address information and write data are held in latches 14 and 16, respectively, in response to the changes of signals AL and DL, respectively. Then at the next cycle, the column decoder operates according to the column address information and the write data held in the preceding cycle, whereby the operation of write driver 8 causes write data to be written into a desired memory cell.
Memory cycle time Tc of a writing operation can also be reduced as described above.
There is particularly no problem in the above described conventional semiconductor memory device carrying out pipe line processing under page mode when the writing operation and the reading operation are respectively continuous. The conventional semiconductor memory device has a disadvantage in operation cycles where the writing operation and the reading operation are alternately switched.
FIG. 19 is a diagram for explaining the operation of each circuit in association with time when the operation cycle changes from the write operation to the read operation in pipe processing in the semiconductor memory device shown in FIG. 11.
First, an external column address and an external data are supplied via address buffer 9 and write buffer 11 to be held in latches 14 and 16, respectively (10-15 ns). At the next cycle, the writing operation is carried out according to the latched column address and write data. Because the reading operation of the next cycle is also carried out at this time, preparation operation for the next reading operation is necessary in this cycle. More specifically, column address B for the reading operation must be provided via address buffer 9 to be latched in latch 14, whereby the column decoder and the preamplifier are operated according to this latched column address. However, firstly the column decoder for writing must be operated in this cycle. The operation of the column decoder must be carried out twice during the cycle of 20 ns-50 ns. These decoder operation can not be carried out simultaneously because there is only one column decoder in a conventional semiconductor memory device. It can not be helped that memory cycle time TA2 required for the first reading operation when changing from the writing operation to the reading operation is longer than memory cycle time TA1 or TA3 of a normal pipe line processing. In order to avoid delay of memory cycle time TA2, a step must be taken to cease the reading operation temporarily, i.e. to process the cycle succeeding the writing cycle as a dummy cycle.
It was therefore not possible to reduce the memory cycle time in switching even if pipe line processing is used in case where the writing operation and the reading operation are frequently switched alternately.